In a semiconductor integrated circuit, a DRAM (dynamic random access memory) having a capacity of less than 4M bits is operated by using a power supply of 5 V. However, the power supply of 5 V cannot be used for a DRAM having a capacity of more than 16M bits, because each memory element is minute for high density to have a thin gate oxide layer, so that the gate oxide layer is degraded due to the application of 5 V. Accordingly, a semiconductor IC having a large capacity DRAM is provided with an internal power supply of 3.3 V for the large capacity DRAM excluding word lines applied with a voltage of 5 V, and with a level conversion output circuit for converting a level of an output signal generated by the internal power supply to 5 V to be adapted to 5 V-logic circuits and then supplied to an external circuit.
A conventional level conversion output circuit includes first (for "high") and second (for "low") level conversion circuits connected to first and second input terminals to be supplied with input signals of "high (3.3 V)" and "low", respectively, a first n-MOS transistor connected at a gate to an output of the first level conversion circuit, and a second n-MOS transistor connected at a gate to an output of the second level conversion circuit. The first n-MOS transistor is connected at a source to a power supply of 5 V and at a drain to an output terminal from which "high (5 V)" and "low" signals are obtained, and the second n-MOS transistor is connected at a source to ground and at a drain to the output terminal. Each of the first and second n-MOS transistors has gate oxide layer having strength against a voltage of 5.5 V, respectively, so that the gate oxide layer is not degraded by a voltage applied from the power supply with a margin of 10%.
The first and second level conversion circuits have the same structure. That is, each of the level conversion circuits is composed of first and second CMOS (complementary metal-oxide semiconductor) inverters which are cascade-connected. The first CMOS inverter is composed of a first p-MOS transistor connected at a source to an internal power supply of 3.3 V and at a gate to the first input terminal, and a third n-MOS transistor connected at a source to ground and at a gate to the first input terminal and at a drain to a drain of the first p-MOS transistor. The second CMOS inverter is composed of a second p-MOS transistor connected at a source to an external power supply of 5 V and at a drain to the gate of the first n-MOS transistor, and a fourth n-MOS transistor connected at a source to ground, at a drain to the gate of the second n-MOS transistor and at a gate to a gate of the second p-MOS transistor. The common drain of the first CMOS inverter is connected to the common gate of the second CMOS inverter.
In operation, in the first level conversion circuit, when a high level signal is supplied to the first input terminal, a low level signal is supplied from the first CMOS inverter to the second CMOS inverter. In response to the low level signal, the second p-MOS transistor is turned on and the fourth n-MOS transistor is turned off, so that a high level signal is supplied to the gate of the first n-MOS transistor. In the second level conversion circuit, when a low level signal is supplied to the second input terminal, a high level signal is supplied from the first CMOS inverter to the second CMOS inverter. In response to the high level signal, the second p-MOS transistor is turned off and the fourth n-MOS transistor is turned on, so that a low level signal is supplied to the gate of the second n-MOS transistor. As the result, a high level output of 5 V is obtained at the output terminal.
In the opposite manner, when a low level signal is supplied to the first input terminal and a high level signal is supplied to the second input terminal, a low level output signal is obtained at the output terminal.
According to the conventional level conversion output circuit, however, there is a disadvantage in that the second p-MOS transistor of the second CMOS inverter can not be completely turned off to cause the flow of current in each second inverter of the first and second level conversion circuits, because "high" signal applied to the gate thereof is 3.3 V, when "low" signals are applied to the first and second input terminals. As a result, power consumption is increased.
Further, when a level of the output terminal is changed from high to low by the inversion of input signals from a state in which "high" and "low" are applied to the first and second input terminals to a state in which "low" and "high" are supplied to the first and second input terminals, a voltage of over 5.5 V is applied to the gate of the second n-MOS transistor in a moment by an overshoot based on the voltage transition of 0 to 5 V. Therefore, the gate oxide layer of the second n-MOS transistor is degraded, a reliability of the semiconductor integrated circuit is lowered.